The present disclosure relates to a semiconductor structure and method for semiconductor fabrication. More specifically the present disclosure relates to, a semiconductor structure and method of semiconductor fabrication for improving lithographic patterning and the transfer of a lithographic pattern into a substrate.
In semiconductor manufacturing, Back End of the Line (BEOL) copper interconnect scaling uses a Trench First Metal Hard Mask (TFMHM) process to maintain pattern fidelity and control during the manufacturing process, for example, from lithography to plasma etch. One motivation known in the art for selecting the Trench First Hard Mask (TFHM) is to eliminate a pass of oxygen type plasma ash that leads to low-k dielectric damage found both in line (trench) sidewalls as well as in vias. A low-κ dielectric material has a lower dielectric constant than silicon dioxide. During processing, a metal hard mask may include a titanium nitride (TiN) film deposited on top of a dielectric hard mask film. Lithographic patterns may be formed on top of the TiN film using organic-containing films. However, undesirable consequences to the trenches of an interconnect structure can occur during the above processing. Thus, TFHM integration results in new challenges with respect to a metal hard mask (e.g., TiN) film's erosion and interaction to plasma during both lithographic rework and dual damascene etching. For example, during a typical rework process, plasma chemistries can both modify the surface and reduce the TiN film thickness which subsequently leads to a wider critical dimension (CD) during a dual damascene etch process step during interconnect processing. Consequently, this results in an undesirable increase in the non-uniformity across a wafer diameter. Moreover, long process queue times between TiN deposition and lithography may occur, and thus, the metallic TiN film forms undesirable native oxides that affect lithography and react with fluorocarbon plasma in such a manner that the control of critical dimension uniformity (CD) of features across the wafer becomes more difficult. Additionally, these mechanisms can create physical defects which affect the overall pattern fidelity.
It is a known difficulty of metal Hardmask process integration techniques, that a metal hardmask such as TiN (Titianium Nitride) sputters during dielectric etch steps of an RIE process. Typical chemistries used during a dielectric etch step of a typical metal Hardmask RIE integration process include: CF4, CHF3, CH2F2, C4F8 with additions of CO2, CO, N2, H2, Ar. These gases physically impact the metal hardmask and both sputter metal into the active patterning space, which potentially results in defects related to a micro-masking of the dielectric by the re-sputtered hardmask material, as well as erode the final physical profile during the RIE profiling process. The problems above result in a RIE process that is difficult to control, and possibly unable to meet the required parameters of the pattern transfer process. For example, the result of the TiN erosion that occurs is a widening of a top trench CD resulting in electrical shorts and reliability degradation.
In semiconductor manufacturing, lithography and plasma etch define the pitch and pattern fidelity of a trench profile. The etch may use polymerizing chemistry to shrink the CD to avoid unwanted CD enlargement. However, a problem with this approach is that the phenomenon of etch bias leads to RIE lag between nested and wide trench lines for both CD and depth. The above occurs because polymerization and etch rate are typically feature size dependent. Variations in pattern transfer can be affected by many parameters, including sidewalls, feature size, pattern density, free mean path, etch chemistries and RIE process parameters, that lead to different polymer deposition thickness as a function of line width. It would therefore be desirable to discourage or reduce uncontrolled surface modification, such as erosion and interaction with plasma, of a metal hardmask, such as a TiN hardmask.